Much attention is given to certain aspects of integrated circuit (IC) technology, such as the number or dimensions of the devices in the circuit and circuit processing speeds that can reach millions of instructions per second (MIPS). Clearly, progress in these areas has great appeal and is readily understood. However, there are other aspects of very large scale integrated (VLSI) circuit technology that are of significant importance. For example, integrated circuits must be electrically contacted to be of any use within a larger electrical circuit. The electrical circuit from the external pins of the integrated circuit package must be connected to the integrated circuit through bond pads that are generally located on the periphery of the integrated circuit. The bond pads, which are typically exposed at the microchip die level, provide the interconnectivity between the integrated circuits on the die and the electrical circuit in which the microchip will be installed. They are generally located on the periphery of the integrated circuit die. Bond pads are metal areas that are electrically connected to the devices within the integrated circuit through buffers and electrically conducting interconnects. While the bond pads are formed during the layering process, wires must ultimately be attached to the bond pads to connect to the external pins of the completed integrated circuit package. As a result of conventional bonding technology, as well as the physical size of the wires and the nature of the bond, the bond pads have relatively large dimensions as compared to device dimensions. Because of their size, the bond pads occupy a significant percentage of the chip surface. The area underneath the bond pads thus occupies a substantial fraction of the entire chip surface.
The electrical connection between the package and the bond pad requires physical integrity as well as high electrical conductivity. The conventional bonding process used to form the connection typically requires elevated temperatures and/or relatively high pressures to produce a good connection between the wire and the bond pad. With the bond pad typically located on top of a dielectric layer, the bonding conditions produce thermal and mechanical stresses in the dielectric. These stresses may cause defects in the dielectric that, in turn, result in large leakage currents through the dielectric between the bond pads and the underlying, electrically-conducting substrate. These leakage currents have traditionally precluded use of the substrate area under the bond pads for active devices, thereby decreasing the device packing fraction. The buffers are typically located on the periphery of the integrated circuit and between bond pads to avoid placement under the bond pads. Similarly, the spacing between bond pads must be increased to accommodate the buffers or other devices.
In the prior art, active circuitry has been successfully constructed in the lower layers of an integrated circuit under the bond pad footprint by depositing a simple metal cushion pad in the metal layer below the bond pad. This metal pad acts as a cushion, protecting the dielectric layers below it from the pressure and heat of the wire bonding process. However, as the technology advances toward even smaller device sizes, which may be on the order of 0.3 or even 0.25 micron, this metal pad loses its effectiveness. Examination of integrated circuits at the 0.3 micron device size, shows cracks in the dielectric in at least 50 percent of the samples. Therefore, it must be concluded that this technology has reached its practical limit at a 0.3 micron device size.
Accordingly, what is needed in the art is an improved method for providing a bond pad support structure that substantially reduces the risk of damage to the circuit structure during the bonding process and allows more efficient use of chip area.